The present invention relates to a semiconductor integrated circuit device, and particularly to a technology effective if applied to a microcomputer mixed in one semiconductor chip with a logical operation circuit and a memory circuit.
A semiconductor integrated circuit device called, for example, a microcomputer is known as a semiconductor integrated circuit device. FIG. 26 is a typical plan view showing a layout of a conventional microcomputer, and FIG. 27 is a typical plan view showing part of FIG. 26 in an enlarged form.
As shown in FIG. 26, the conventional microcomputer is principally made up of a semiconductor chip 30 whose plane surface is square. An internal circuit forming section 2 is disposed in a central portion of a main surface of the semiconductor chip 30. Circuit blocks such as a logical operation circuit, a memory circuit, etc. are disposed in the internal circuit forming section 2 in plural form.
Four input/output cell forming sections 3 are disposed outside the internal circuit forming section 2 in association with the respective sides of the semiconductor chip 30. A plurality of bonding pads 9 are disposed outside the four input/output cell forming sections 3 along the respective sides of the semiconductor chip 30. As shown in FIG. 27, a plurality of input/output cells 4 are disposed in the four input/output cell forming sections 3 along their corresponding sides of the semiconductor chip 30. The input/output cells 4 are respectively disposed corresponding to the bonding pads 9.
Power supply wirings 8a for internal circuit, for supplying potentials to the internal circuit forming section 2 are disposed outside the internal circuit forming section 2 and outside the input/output cells 4. The power supply wirings 8a are shaped in the form of a ring that continuously extends over the periphery of the internal circuit forming section 2.
Power supply wirings 8b for input/output cells, for respectively supplying potentials to the input/output cells 4 are disposed outside the power supply wirings 8a and inside the bonding pads 9. The power supply wirings 8b are shaped in the form of a ring that continuously extends over the plural input/output cells 4 so as to surround the internal circuit forming section 2.
The plural input/output cells 4 include signal cells 5, power supply cells 6a for internal circuit, and power supply cells 6b for input/output cells. The plural bonding pads 9 include signal pads 10 respectively disposed corresponding to the signal cells 5 and electrically connected to the signal cells 5, power supply pads 11a for internal circuit, which are respectively disposed corresponding to the power supply cells 6a and electrically connected to the power supply cells 6a and the power supply wirings 8a, and power supply pads 11b for input/output cells, which are respectively disposed corresponding to the power supply cells 6b and electrically connected to the power supply cells 6b and the power supply wirings 8b. 
Meanwhile, in the microcomputer, the number of bonding pads goes on increasing with its multifunctioning and high integration. In the microcomputer wherein the plural bonding pads 9 are disposed along the respective sides of the semiconductor chip as shown in FIG. 26, a plane size becomes large with an increase in the number of the bonding pads. Consequently, a technology for contriving the layout of bonding pads to thereby bring a semiconductor integrated circuit device into less size has been disclosed in Japanese Unexamined Patent Publication No. Hei 11(1999)-40754 (patent document 1 shown below). A technology for disposing a plurality of bonding pads along each side of a semiconductor chip in zigzag form has been described in the present patent document 1. As shown in FIG. 4 of the same patent document 1 and described in the paragraph number [0014] in the description of FIG. 4, the technology is also described in the patent document 1, that “outer peripheral and inner peripheral bonding pads 1a and 1b are used only for signals, and the innermost peripheral bonding pads 4 and 5 disposed inner than each buffer area are used only for a power supply and ground. Therefore, since all of areas conventionally secured in the buffer areas as for the power supply and ground can be used for a signal buffer 2, the size of the semiconductor chip can be reduced without depending on the numbers of power supply and ground pins that need to be provided over the chip. Further, the width of each of wirings 3 for connecting the outer peripheral and inner peripheral bonding pads 1a and 1b and buffer 2 can be sufficiently ensured”.
Patent Document 1
Japanese Unexamined Patent Publication No. Hei 11(1999)-40754.